1. Field of the Invention
The present invention relates to MOS transistors and more particularly to the protection of output MOS transistors included in integrated circuits against overvoltages such as electrostatic pulses.
2. Discussion of the Related Art
FIG. 1 is a cross-sectional view of an exemplary conventional structure of an N-channel MOS transistor used in an integrated circuit. The MOS transistor comprises a conductive gate region 1 on an isolating gate layer 2. On both sides of the gate region are formed an N.sup.+ drain region 3 and an N.sup.+ source region 4, respectively. These regions are formed in a low doped P-type region, layer or well 5, in turn formed on a highly doped P-type layer or substrate 6. During operation of the MOS transistor, regions 5 and 6 are biased at a reference voltage. A highly doped P-type region 7 contacts region 5.
FIG. 2 shows a conventional output stage of a MOS integrated circuit of the CMOS (complementary MOS) type. This stage comprises an N-type MOS (NMOS) transistor having its source terminal connected to a low voltage or reference voltage Vss in series with a P-channel MOS (PMOS) transistor having its source terminal connected to a high voltage Vdd. The common drain of transistors NMOS and PMOS forms the output which is provided at terminal A. Thus, output terminal A is at a high voltage when the PMOS transistor only is conductive and is at a low voltage when the NMOS transistor only is conductive.
When the N-channel MOS transistor of FIG. 1 is used as the NMOS transistor of FIG. 2, its drain region 3 is connected to output A. The source region 4 and the substrate contacting region 7 (which are in contact with each other) are interconnected to low voltage Vss. G designates the gate terminal of the NMOS transistor of FIG. 2.
A problem exists in that a MOS transistor includes a parasitic bipolar transistor, the collector of which corresponds to drain region 3, the emitter to source region 4, and the base to region 5. Owing to the presence of the resistive connection between the base (region 5) and the emitter (region 4), this transistor can go into avalanche mode when the current in region 5 becomes high, which may occur due to a current surge caused by an electrostatic pulse from the supply terminal Vdd or output terminal A. This avalanching mode can, if no current clipping is provided, cause the destruction of the component resulting either from destruction of the gate isolating layer 2 or piercing of the drain junction resulting from the migration of the drain metallization coating (not shown).
Therefore, various protection circuits have been provided in the prior art to avoid these problems.